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1 features ? single voltage operation ?5v read ? 5v reprogramming fast read access time ? 55 ns internal program control and timer sector architecture ? one 16k bytes boot block with programming lockout ? two 8k bytes parameter blocks ? two main memory blocks (32k, 64k bytes) fast erase cycle time ? 10 seconds byte-by-byte programming ? 10 s/byte typical hardware data protection data polling for end of program detection low power dissipation ? 50 ma active current ? 100 a cmos standby current typical 10,000 write cycles description the at49f001(n)(t) is a 5-volt only in-system reprogrammable flash memory. its 1 megabit of memory is organized as 131,072 words by 8 bits. manufactured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 1-megabit (128k x 8) 5-volt only flash memory at49f001 at49f001n at49f001t at49f001nt rev. 1008d?flash?2/03 plcc top view pin configurations pin name function a0 - a16 addresses ce chip enable oe output enable we write enable reset reset i/o0 - i/o7 data inputs/outputs nc no connect dc don?t connect 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 a16 reset * vcc we nc dip top view vsop top view (8 x 14 mm) or tsop top view (8 x 20 mm) type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 * reset a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we nc a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 nc we vcc * reset a16 a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 note: *this pin is a dc on the at49f001n(t).
2 at49f001(n(t) 1008d?flash?2/03 55 ns with power dissipation of just 275 mw over the commercial temperature range. when the device is deselected, the cmos standby current is less than 100 a. for the at49f001n(t) pin 1 for the dip and plcc packages and pin 9 for the tsop package are don?t connect pins. to allow for simple in-system reprogrammab ility, the at49f001(n)(t) does not require high input voltages for programming. five-volt-only commands determine the read and program- ming operation of the device. reading data out of the device is similar to reading from an eprom; it has standard ce , oe , and we inputs to avoid bus contention. reprogramming the at49f001(n)(t) is performed by erasing a block of data and then programming on a byte-by- byte basis. the byte programming time is a fast 50 s. the end of a program cycle can be optionally detected by the data polling feature. once the end of a byte program cycle has been detected, a new access for a read or program can begin. the typical number of program and erase cycles is in excess of 10,000 cycles. the device is erased by execut ing the erase command sequence; the device internally con- trols the erase operations. there are two 8k bytes parameter block sections and two main memory blocks. the device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. the 16-kbyte boot block section includes a reprogramming lock out fea- ture to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed. in the at49f001(n)(t), once the boot block programming lockout feature is enabled, the con- tents of the boot block are permanent and cannot be changed. in the at49f001(t), once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of 5.5 volts or less. block diagram control logic y decoder parameter block 1 (8k bytes) boot block (16k bytes) oe we ce reset address inputs vcc gnd at49f001(n)t data inputs/outputs i/o7 - i/o0 8 x decoder parameter block 2 (8k bytes) main memory block 1 (32k bytes) main memory block 2 (64k bytes) program data latches y-gating input/output buffers 1ffff 1c000 1bfff 1a000 19fff 18000 17fff 10000 0ffff 00000 parameter block 1 (8k bytes) boot block (16k bytes) at49f001(n) data inputs/outputs i/o7 - i/o0 8 parameter block 2 (8k bytes) main memory block 1 (32k bytes) main memory block 2 (64k bytes) program data latches y-gating input/output buffers 1ffff 10000 0ffff 08000 07fff 06000 05fff 04000 03fff 00000
3 at49f001(n(t) 1008d?flash?2/03 device operation read: the at49f001(n)(t) is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. command sequences: when the device is first powered on, it will be reset to the read or standby mode depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the command definitions table. the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address locations used in the command sequences are not affected by entering the com- mand sequences. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high inpendance state. if the reset pin makes a high-to-low transition during a program or erase operation, the operation may not be successfully completed and the operation will have to be repeated after a high level is applied to the reset pin. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. by applying a 12v 0.5v input signal to the reset pin, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see boot block pro- gramming lockout override section). the reset feature is not available for the at49f001n(t). erasure: before a byte can be reprogrammed, the main memory block or parameter block which contains the byte must be erased. the erased state of the memory bits is a logical ?1?. the entire device can be erased at one time by using a 6-byte software code. the software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the chip erase cycle waveforms). after the software chip erase has been initiated, the device will internally time the erase opera- tion so that no external clocks are required. the maximum time needed to erase the whole chip is t ec . if the boot block lockout feature has been enabled, the data in the boot sector will not be erased. chip erase: if the boot block lockout has been enabled, the chip erase function will erase parameter block 1, parameter block 2, main memory block 1, and main memory block 2 but not the boot block. if the boot block lockout has not been enabled, the chip erase function will erase the entire chip. after the full chip erase the device will return back to read mode. any command during chip erase will be ignored.
4 at49f001(n(t) 1008d?flash?2/03 sector erase : as an alternative to a full chip eras e, the device is organized into sectors that can be individually erased. there are two 8-kbyte parameter block sections and two main memory blocks. the 8-kbyte parameter block sections can be independently erased and reprogrammed. the two main memory sections are designed to be used as alternative mem- ory sectors. that is, whenever one of the blocks has been erased and reprogrammed, the other block should be erased and reprogrammed before the first block is again erased. the sector erase command is a six bus cycle operation. the sector address is latched on the fall- ing we edge of the sixth cycle while the 30h data input command is latched at the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase opera- tion is internally controlled; it will automatically time to completion. byte programming: once the memory array is erased, the device is programmed (to a logical ?0?) on a byte-by-byte basis. please note that a data ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the command definitions table). the device will automatically generate the required internal program pulses. the program cycle has addresses latched on the falling edge of we or ce , whichever occurs last, and the data latched on the rising edge of we or ce , whichever occurs first. program- ming is completed after the specified t bp cycle time. the data polling feature may also be used to indicate the end of a program cycle. boot block programming lockout: the device has one designated block that has a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. the size of the block is 16k bytes. this block, referred to as the boot block, can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; the boot block?s usage as a write protected region is optional to the user. the address range of the boot block is 00000 to 03fff for the at49f001(n) while the address range of the boot block is 1c000 to 1ffff for the at49f001(n)t. once the feature is enabled, the data in the boot block can no longer be erased or pro- grammed with input voltage levels of 5.5v or less. data in the main memory block can still be changed through the regular programming method. to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. please refer to the command definitions table. boot block lockout detection: a software method is available to determine if pro- gramming of the boot block section is locked out. when the device is in the software product identification mode (see software product ident ification entry and exit sections) a read from address location 00002h will show if programming the boot block is locked out for the at49f001(n) and a read from address 1c002h will show if programming the boot block is locked out for the at49f001(n)t. if the data on i/o0 is low, the boot block can be pro- grammed; if the data on i/o0 is high, the program lockout feature has been activated and the block cannot be programmed. the software product identification exit code should be used to return to standard operation.
5 at49f001(n(t) 1008d?flash?2/03 boot block programming lockout override: the user can override the boot block programming lockout by taking the reset pin to 12 volts. by doing this, protected boot block data can be altered through a chip erase, sector erase or word programming. when the reset pin is brought back to ttl levels the boot block programming lockout feature is again active. this feature is not available on the at49f001n(t). product identification: the product identification mode identifies the device and man- ufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at49f001(n)(t) features data polling to indicate the end of a pro- gram cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling the at49f001(n)(t) provides another method for determining the end of a program or erase cycle. during a program or erase operation, suc- cessive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. hardware data protection: hardware features protect against inadvertent programs to the at49f001(n)(t) in the following ways: (a) v cc sense: if v cc is below 3.8v (typical), the program function is inhibited. (b) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (c) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle.
6 at49f001(n(t) 1008d?flash?2/03 notes: 1. the data format in each bus cycle is as follows: i/o7 - i/o0 (hex) 2. the 16k byte boot sector has the address range 00000h to 03fffh for the at49f001(n) and 1c000h to 1ffffh for the at49f001(n)t. 3. either one of the product id exit commands can be used. 4. sa = sector addresses for the at49f001(n): sa = 00000 to 03fff for boot block nothing will happen and the device goes back to the read mode in 100 ns sa = 04000 to 05fff for parameter block 1 sa = 06000 to 07fff for parameter block 2 sa = 08000 to 0ffff for main memory array block 1 this command will erase - pb1, pb2 and mmb1 sa = 10000 to 1ffff for main memory array block 2 for the at49f001(n)t: sa = 1c000 to 1ffff for boot block nothing will happen and the device goes back to the read mode in 100 ns sa = 1a000 to 1bfff for parameter block 1 sa = 18000 to 19fff for parameter block 2 sa = 10000 to 17fff for main memory array block 1 this command will erase - pb1, pb2 and mmb1 sa = 00000 to 0ffff for main memory array block 2 absolute maximum ratings* command definition (in hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (4) 30 byte program 4 5555 aa 2aaa 55 5555 a0 addr d in boot block lockout (2) 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (3) 3 5555 aa 2aaa 55 5555 f0 product id exit (3) 1 xxxx f0 temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
7 at49f001(n(t) 1008d?flash?2/03 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1fh, device code: 05h - at49f001(n), 04h - at49f001(n)t 5. see details under software product identification entry/exit. 6. this pin is not available on the at49f001n(t). note: 1. in the erase mode, i cc is 90 ma. dc and ac operating range at49f001(n)(t)-55 at49f001(n)(t)-70 at49f001(n)(t)-90 at49f001(n)(t)-12 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% operating modes mode ce oe we reset (6) ai i/o read v il v il v ih v ih ai d out program/erase (2) v il v ih v il v ih ai d in standby/write inhibit v ih x (1) xv ih x high z program inhibit x x v ih v ih program inhibit x v il xv ih output disable x v ih xv ih high z reset x x x v il x high z product identification hardware v il v il v ih a1 - a16 = v il , a9 = v h , (3) a0 = v il manufacturer code (4) a1 - a16 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) a0 = v il , a1 - a16=v il manufacturer code (4) a0 = v ih , a1 - a16=v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc com. 100 a ind. 300 a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage cmos i oh = -100 a; v cc = 4.5v 4.2 v
8 at49f001(n(t) 1008d?flash?2/03 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at49f001(n)(t)-55 at49f001(n)(t)-70 at49f001(n)(t)-90 at49f001(n)(t)-12 units min max min max min max min max t acc address to output delay 55 70 90 120 ns t ce (1) ce to output delay 55 70 90 120 ns t oe (2) oe to output delay 0 30 0 35 0 40 0 50 ns t df (3)(4) ce or oe to output float 0 25 0 25 0 25 0 30 ns t oh output hold from oe , ce or address, whichever occurred first 000 0ns address output high z output oe ce t acc t oe t df t oh t ce valid address valid
9 at49f001(n(t) 1008d?flash?2/03 input test waveform and measurement level t r , t f < 5 ns output load test note: 1. this parameter is characterized and is not 100% tested. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v 5.0v 1.8k 100 pf 30 pf 1.3k 5.0v 1.8k output pin 1.3k output pin 55 ns 70/90/120 ns
10 at49f001(n(t) 1008d?flash?2/03 ac byte load waveforms we controlled ce controlled ac byte load characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 90 ns t dh t ds t as t ah t wp ce address data in oe t oes t oeh we t cs t ch t wph t dh t ds t as t ah t wp we address data in oe t oes t oeh ce t cs t ch t wph
11 at49f001(n(t) 1008d?flash?2/03 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 5555. for sector erase, the address depends on what sector is to be erased. (see note 4 under command definitions.) 3. for chip erase, the data should be 10h, and for sector erase, the data should be 30h. program cycle characteristics symbol parameter min typ max units t bp byte programming time 10 50 s t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 90 ns t wph write pulse width high 90 ns t ec erase cycle time 10 seconds oe program cycle input data address a0 55 5555 5555 aa 2aaa t bp t wph t wp ce we a0-a16 data t as t ah t dh t ds oe (1) aa 80 note 3 55 55 5555 5555 note 2 aa byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 2aaa 2aaa t wph t wp ce we a0-a16 data t as t ah t ec t dh t ds 5555
12 at49f001(n(t) 1008d?flash?2/03 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns high z an an an an an we ce oe i/o7 a0-a16 t oeh t oe t dh t wr we ce oe i/o6 t oeh high z t dh t oe t wr t oehp
13 at49f001(n(t) 1008d?flash?2/03 software product identification entry (1) software product identification exit (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a16 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1fh device code: 05h - at49f001(n) 04h - at49f001(n)t load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) boot block lockout feature enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. boot block lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 1 second (2)
14 at49f001(n(t) 1008d?flash?2/03 at49f001 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 55 50 0.1 at49f001-55jc at49f001-55pc at49f001-55tc at49f001-55vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001-55ji at49f001-55pi at49f001-55ti at49f001-55vi 32j 32p6 32t 32v industrial (-40 to 85 c) 70 50 0.1 at49f001-70jc at49f001-70pc at49f001-70tc at49f001-70vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001-70ji at49f001-70pi at49f001-70ti at49f001-70vi 32j 32p6 32t 32v industrial (-40 to 85 c) 90 50 0.1 at49f001-90jc at49f001-90pc at49f001-90tc at49f001-90vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001-90ji at49f001-90pi at49f001-90ti at49f001-90vi 32j 32p6 32t 32v industrial (-40 to 85 c) 120 50 0.1 at49f001-12jc at49f001-12pc at49f001-12tc at49f001-12vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001-12ji at49f001-12pi at49f001-12ti at49f001-12vi 32j 32p6 32t 32v industrial (-40 to 85 c) package type 32j 32-lead, plastic, j-leaded chip carrier package (plcc) 32p6 32-lead, 0.600" wide, plastic dual in-line package (pdip) 32t 32-lead, plastic thin small outline package (tsop) 32v 32-lead, plastic thin small outline package (vsop) (8 x 14 mm)
15 at49f001(n(t) 1008d?flash?2/03 at49f001n ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 55 50 0.1 at49f001n-55jc at49f001n-55pc at49f001n-55tc at49f001n-55vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001n-55ji at49f001n-55pi at49f001n-55ti at49f001n-55vi 32j 32p6 32t 32v industrial (-40 to 85 c) 70 50 0.1 at49f001n-70jc AT49F001N-70PC at49f001n-70tc at49f001n-70vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001n-70ji at49f001n-70pi at49f001n-70ti at49f001n-70vi 32j 32p6 32t 32v industrial (-40 to 85 c) 90 50 0.1 at49f001n-90jc at49f001n-90pc at49f001n-90tc at49f001n-90vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001n-90ji at49f001n-90pi at49f001n-90ti at49f001n-90vi 32j 32p6 32t 32v industrial (-40 to 85 c) 120 50 0.1 at49f001n-12jc at49f001n-12pc at49f001n-12tc at49f001n-12vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001n-12ji at49f001n-12pi at49f001n-12ti at49f001n-12vi 32j 32p6 32t 32v industrial (-40 to 85 c) package type 32j 32-lead, plastic, j-leaded chip carrier package (plcc) 32p6 32-lead, 0.600" wide, plastic dual in-line package (pdip) 32t 32-lead, plastic thin small outline package (tsop) 32v 32-lead, plastic thin small outline package (vsop) (8 x 14 mm)
16 at49f001(n(t) 1008d?flash?2/03 at49f001t ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 55 50 0.1 at49f001t-55jc at49f001t-55pc at49f001t-55tc at49f001t-55vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001t-55ji at49f001t-55pi at49f001t-55ti at49f001t-55vi 32j 32p6 32t 32v industrial (-40 to 85 c) 70 50 0.1 at49f001t-70jc at49f001t-70pc at49f001t-70tc at49f001t-70vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001t-70ji at49f001t-70pi at49f001t-70ti at49f001t-70vi 32j 32p6 32t 32v industrial (-40 to 85 c) 90 50 0.1 at49f001t-90jc at49f001t-90pc at49f001t-90tc at49f001t-90vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001t-90ji at49f001t-90pi at49f001t-90ti at49f001t-90vi 32j 32p6 32t 32v industrial (-40 to 85 c) 120 50 0.1 at49f001t-12jc at49f001t-12pc at49f001t-12tc at49f001t-12vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001t-12ji at49f001t-12pi at49f001t-12ti at49f001t-12vi 32j 32p6 32t 32v industrial (-40 to 85 c) package type 32j 32-lead, plastic, j-leaded chip carrier package (plcc) 32p6 32-lead, 0.600" wide, plastic dual inline package (pdip) 32t 32-lead, plastic thin small outline package (tsop) 32v 32-lead, plastic thin small outline package (vsop) (8 x 14 mm)
17 at49f001(n(t) 1008d?flash?2/03 at49f001nt ordering information t acc (ns) i cc (ma) ordering code package operation range 55 50 0.1 at49f001nt-55jc at49f001nt-55pc at49f001nt-55tc at49f001nt-55vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001nt-55ji at49f001nt-55pi at49f001nt-55ti at49f001nt-55vi 32j 32p6 32t 32v industrial (-40 to 85 c) 70 50 0.1 at49f001nt-70jc at49f001nt-70pc at49f001nt-70tc at49f001nt-70vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001nt-70ji at49f001nt-70pi at49f001nt-70ti at49f001nt-70vi 32j 32p6 32t 32v industrial (-40 to 85 c) 90 50 0.1 at49f001nt-90jc at49f001nt-90pc at49f001nt-90tc at49f001nt-90vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001nt-90ji at49f001nt-90pi at49f001nt-90ti at49f001nt-90vi 32j 32p6 32t 32v industrial (-40 to 85 c) 120 50 0.1 at49f001nt-12jc at49f001nt-12pc at49f001nt-12tc at49f001nt-12vc 32j 32p6 32t 32v commercial (0 to 70 c) 50 0.3 at49f001nt-12ji at49f001nt-12pi at49f001nt-12ti at49f001nt-12vi 32j 32p6 32t 32v industrial (-40 to 85 c) package type 32j 32-lead, plastic, j-leaded chip carrier package (plcc) 32p6 32-lead, 0.600" wide, plastic dual in-line package (pdip) 32t 32-lead, plastic thin small outline package (tsop) 32v 32-lead, plastic thin small outline package (vsop) (8 x 14 mm)
18 at49f001(n(t) 1008d?flash?2/03 packaging information 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
19 at49f001(n(t) 1008d?flash?2/03 32p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32p6 , 32-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 32p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 41.783 ? 42.291 note 1 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 1 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
20 at49f001(n(t) 1008d?flash?2/03 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
21 at49f001(n(t) 1008d?flash?2/03 32v ? vsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32v , 32-lead (8 x 14 mm package) plastic thin small outline package, type i (vsop) b 32v 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation ba. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 13.80 14.00 14.20 d1 12.30 12.40 12.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
printed on recycled paper. atmel ? is the registered trademark of atmel. other terms and product names may be the trademarks of others. ? atmel corporation 2003. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on t he company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change de vices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, ex pressly or by implication. at mel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 1008d?flash?2/03 xm

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